Fault-tolerant quantum computing developer Alice & Bob has presented proof-of-concept results demonstrating the decoding of its LDPC-cat quantum error correction architecture on NVIDIA GPUs using the low-latency NVQLink system architecture.
The demonstration evaluated the transfer of synthetic measurement data from Quantum Machines’ OPX1000 control hardware to GPUs using the Open Acceleration Stack, establishing microsecond-scale roundtrip communication pathways between quantum control systems and classical GPU supercomputers. NVQLink provides a high-throughput, tight-coupling interface designed to accelerate real-time error-correction decoding, calibration, and hybrid quantum-classical workloads.
| [ Technical Integration Parameters & Milestones ] | ||
|---|---|---|
| Integration Layer | Hardware & Software Framework | Operational Functionality |
| • QPU Control Hardware | • Quantum Machines OPX1000 | • Streams quantum syndrome measurements through the Open Acceleration Stack. |
| • Interconnect Architecture | • NVIDIA NVQLink | • Delivers microsecond-scale, high-bandwidth communication between QPUs and GPUs. |
| • Error Correction Code | • 2D LDPC-Cat Codes | • Combines physical bit-flip protection of cat qubits with low-overhead 2D qLDPC layouts. |
| • Parallel Decoding | • NVIDIA GPU Clusters | • Decodes multiple syndrome streams in parallel to scale decoding throughput alongside QPU size. |
Alice & Bob’s LDPC-cat architecture leverages cat qubits, which inherently suppress physical bit-flip errors exponentially through continuous non-linear dissipation. By pairing cat qubits with 2D low-density parity-check (LDPC) codes, the architecture enables 100 logical qubits to be implemented on a 758 cat-qubit chip with logical error rates below 10-8 per cycle.
Although the initial demonstration utilized synthetic data off-line rather than real-time QPU feedback, it validates parallel syndrome decoding efficiency across GPU clusters, building upon Alice & Bob’s decoupled AI control topologies to resolve microsecond latencies for cat qubits and Bull’s partnership to integrate cat qubit processors into HPC supercomputing infrastructure.
Review the announcement on the Alice & Bob Newsroom here and examine the foundational 2D LDPC-cat architecture research in Nature Communications here.
October 14, 2026