The European Union’s Chips Joint Undertaking (Chips JU) has launched Q-PLANET, a €50 million ($57.2 million USD) European Quantum Chip Stability Pilot Line dedicated to manufacturing industrial-grade components for neutral atom quantum computing, sensing, and communication platforms. Coordinated by hardware developer Pasqal, the initiative establishes a pan-European fabrication backbone across 28 Research and Technology Organizations (RTOs), academic groups, and industrial partners spanning 11 EU Member States.
Structured under a six-year Framework Partnership Agreement, the project aims to resolve the scalability bottlenecks of near-term quantum processors by establishing standardized, replicable semiconductor design and assembly pipelines.
Manufacturing Standardization via PDK and ADK Frameworks
The transition of neutral atom quantum hardware from custom laboratory assemblies into high-volume manufacturing is limited by a lack of standardized manufacturing control loops and system calibration baselines. Q-PLANET is tasked with bridging this operational gap by designing, fabricating, and verifying chip-based hardware sub-systems.
During its initial three-year phase, the consortium will optimize three core product categories:
- Laser-on-Chip Systems: Fabricating integrated laser sources and amplifiers operating across four critical wavelengths—461 nm, 698 nm, 795 nm, and 1013 nm—necessary for the trap manipulation, cooling, and state readout of neutral atom qubits (such as strontium and ytterbium).
- Advanced Atom Chips: Designing microfabricated planar chips for atomic containment, lowering the footprint and power budgets required for scalable Quantum Processing Units (QPUs).
- Microfabricated Vapor Cells: Developing miniature, chip-scale gas cells featuring internal electrodes and anti-relaxation coatings to support atomic clocks, quantum memories, and Rydberg-based electromagnetic field sensors.
To lower market entry barriers for startups and SMEs, Q-PLANET will formalize these microfabrication pipelines into open, standard Process Design Kits (PDKs) and Assembly Design Kits (ADKs). These toolkits provide hardware engineers with pre-validated component layouts and automated assembly guidelines, decoupling hardware design from custom cleanroom engineering.
Cross-Border Foundry Networks and Infrastructure Roles
The consortium distributes its semiconductor foundry, software integration, and packaging responsibilities across specialized centers to build supply chain resilience within the European semiconductor sector:
- Silicon Nitride (SiN) Foundries: The Technical University of Denmark (DTU) leverages its cleanroom infrastructure to serve as the passive optical element foundry for the 461 nm and 795 nm bands. Concurrently, the VTT Technical Research Centre of Finland operates the foundry and testing lines for 1013 nm SiN devices, while leading the active chip-to-fiber pigtailing and packaging work package.
- III-V Semiconductor Fab: TopGaN and the Institute of High Pressure Physics of the Polish Academy of Sciences (Unipress) manage the design, wafer-level characterization, and processing of gallium nitride emitters for the 461 nm blue laser lines. III-V Lab provides parallel design and foundry support for the 795 nm and 1013 nm architectures.
- Control Middleware & APIs: To unify the control layer, iQrypto is building a standardized Linux API and common middleware layer over its software stack. This provides a uniform software interface for end-users to interact with the high-speed electronic modulators and FPGA-driven pulse controllers managing the quantum components.
- Metrological Verification: The Istituto Nazionale di Ricerca Metrologica (INRiM) in Italy leads the noise and linewidth validation tests across all four target wavelengths, utilizing narrow optical filters and metrological clocks to certify physical qubit performance boundaries.
The integrated components will be systematically validated on active testing beds, including Pasqal’s commercial neutral atom QPUs, the University of Stuttgart‘s QRydDemo demonstrator platform, and Welinq’s quantum memory nodes. By evaluating energy consumption metrics alongside architectural performance, the program seeks to mature the target hardware from Technology Readiness Level 4 (TRL 4) up to industrial validation at TRL 6.
Review the official launch documentation and consortium breakdown via the Pasqal Newsroom. Industrial and academic specifications tracking the development of the open process kits can be explored on the official Q-PLANET hub.
July 13, 2026