Quantum software company Classiq and quantum architecture developer ParityQC have announced a strategic partnership to integrate ParityQC’s proprietary Parity Twine compiler technology directly with Classiq’s quantum software engineering platform.
Supported by the German Federal Ministry for Economic Affairs and Climate Action (BMWK) based on a decision by the German Bundestag, the Germany-Israel cross-border initiative aims to resolve a critical scalability challenge: executing complex algorithms on physical processors with limited physical qubit connectivity.
[ Classiq & ParityQC Integration ]
Software Host ──► Classiq's model-first quantum software engineering platform.
Architecture Engine ──► ParityQC's Parity Twine routing and compiler tools.
Target Problem ──► Hardware-aware circuit compilation and SWAP gate minimization.
Funding Vehicle ──► Supported by the German Federal Ministry for Economic Affairs & Climate Action.
Addressing the Hardware Connectivity Bottleneck
When executing high-level quantum algorithms, developers must translate abstract mathematical logic into physical gate instructions. In NISQ (Noisy Intermediate-Scale Quantum) devices, physical qubits cannot connect to all other qubits at will. Traditionally, compilers overcome this limitation by inserting chains of costly SWAP gates to route information across a 2D layout. However, each SWAP operation introduces physical gate errors, increasing overall circuit depth and accelerating environmental decoherence (phase decay).
The collaboration addresses this routing bottleneck by combining Classiq’s universal optimization protocol with ParityQC’s algorithm-aware compilation:
- SWAP Gate Minimization: The integration maps high-level functional circuit descriptions onto specific physical hardware topologies, identifying optimal routing patterns that eliminate unnecessary gate overhead.
- Preserving Software Portability: Classiq’s model-first abstraction layer allows developers to write hardware-agnostic applications, while ParityQC’s compiler backend handles the machine-specific physical translation.
- Demonstrated Performance Gains: In recent hardware benchmarks, running Parity Twine on an IBM Quantum Heron processor achieved a new world-record implementation for the Quantum Fourier Transform (QFT), nearly doubling the performance of previous routing benchmarks.
By embedding hardware-aware compilation directly into high-level development environments, the partnership lowers the physical engineering barriers for enterprise teams building algorithms. The combined infrastructure provides a unified, automated path to optimize and run quantum programs across rapidly evolving hardware platforms, from noisy current systems to future fault-tolerant systems.
Review the official corporate collaboration announcement via the ParityQC Pressroom here.
July 15, 2026