D-Wave Quantum Inc. (NYSE: QBTS) has announced a new strategic development initiative focused on advanced cryogenic packaging. This initiative is designed to improve packaging capabilities, equipment, and processes, with the aim of advancing and scaling both gate model and annealing quantum processor development. The effort builds on D-Wave’s technology in superconducting cryogenic packaging.
As part of this initiative, D-Wave is leveraging expertise and processes at the NASA Jet Propulsion Laboratory (JPL), which is federally funded by NASA and managed by Caltech. Utilizing JPL’s superconducting bump-bond process, D-Wave has demonstrated end-to-end superconducting interconnect between chips. This work is intended as a foundation for scaling D-Wave’s annealing architectures and its fluxonium-based gate-model architectures, as superconducting bump bonds are considered relevant for scalable control and interconnectivity in multichip quantum processor architectures. D-Wave is also acquiring equipment and developing processes to increase circuit densities in its superconducting printed-circuit-board (PCB) manufacturing.
This initiative aims to accelerate D-Wave’s cross-platform technology development efforts while maintaining and expanding fundamental components of its supply chain. The development is positioned to support scaling quantum systems toward larger qubit counts, relevant for both annealing and gate-model approaches, including the company’s goal towards 100,000 qubits. The efforts are also intended to support coherence times that meet the requirements for error-corrected gate-model quantum computing technology, addressing the demanding requirements of quantum processor packaging such as ultra-low temperature operation, extremely low magnetic fields, and fully superconducting interconnects.
Read the full announcement here.
July 30, 2025
