Hardware developer IonQ, Inc. has reported the simultaneous experimental execution of nine distinct quantum error-correcting codes across three structural families—quantum low-density parity-check (qLDPC) codes, topological codes, and concatenated codes—compiled onto a single, non-reconfigured trapped-ion processor. Detailed in a technical manuscript deposited on the open-access arXiv repository, the research team utilized a linear chain of forty barium (133Ba+) isotopes to evaluate alternative memory schemes against nearest-neighbor planar boundaries. By exploiting the all-to-all connectivity native to trapped-ion systems, the architectural demonstration achieved operational breakeven lifetimes, a parameter space where a composite logical qubit’s state survival time matches or slightly exceeds the coherence baseline of its constituent physical qubits.
Optical-Metastable-Ground Shuttling and Pipelined Syndrome Extraction
To execute repeated stabilizer measurement rounds without the severe spatial transport and sympathetic cooling overheads typical of traditional trapped-ion architectures, the processor leverages a specialized implementation of the Optical-Metastable-Ground (OMG) atomic level structure. Physical qubits are initialized and manipulated within the ground manifold using steerable 532 nm Raman beams, but during mid-circuit measurement blocks, a global 1762 nm laser shelves spectator data qubits into the metastable manifold to shield them from environmental optical crosstalk. Readout ancillae are then selectively deshelved back to the ground state for parallel fluorescence collection, functioning as simultaneous measurement channels and in-place sympathetic cooling nodes. This integrated dual-purpose configuration completely eliminates the need for dedicated coolant ion species or localized spatial shuttling routines, compressing the physical cycle duration down to a pipelined window defined by consolidated readout operations.
Stabilizer Code Performance and Decoherence Control Metrics
The error-corrected memory experiments evaluated code capacities across progressive syndrome intervals, applying a classical minimum-weight perfect matching beam decoder to reconstruct accumulated noise vectors. When configured to drive a bivariate bicycle BB5 qLDPC code—which wraps four logical qubits into eighteen physical containers—the architecture achieved a logical error rate per cycle that is four times lower for Z-basis errors and nine times lower for X-basis errors relative to prior solid-state superconducting transmon implementations utilizing long-range hardware couplers. Under strict, non-post-selected channel decay speed definitions, the highest-performing configuration emerged from a weight-5 generalized GB4 qLDPC matrix, yielding a total logical memory lifetime of 3.95 seconds compared to the underlying physical qubit relaxation baseline of 1.1 seconds.
The detailed hardware-software co-design manuscript can be accessed directly via the open-access arXiv repository here.
June 6, 2026
