Google Quantum AI has introduced Willow, a cutting-edge quantum chip that marks significant advancements in quantum computing. The 105-qubit chip achieves state-of-the-art superconducting qubit performance and the company has reported on two key demonstrations they have performed with this new chip.
- New Levels of Performance in the Random Circuit Sampling (RCS) benchmark. In 2019, a previous generation Sycamore chip demonstrated an implementation of a Random Circuit Sampling (RCS) that achieved in about 3 minutes a problem that would take one of the fastest supercomputers about 10,000 years to solve. Since then, both the classical algorithms as well as the classical supercomputer hardware have improved significantly. But now in 2024, Willow completed a computation in under five minutes that would take the largest current day classical supercomputer 1025 years to finish, far exceeding the age of the universe. This result underscores the vast computational advantage of quantum systems over classical counterparts.
- Exponential Error Reduction: Willow demonstrates a scalable quantum error correction method, achieving an exponential reduction in error rates with larger qubit grids. For the first time, a system operates “below threshold,” indicating error correction that enhances overall system performance as the number of qubits increases. This milestone, pursued for nearly three decades, is crucial for building scalable, practical quantum computers.
Google has made several improvements with the Willow chip over the predecessor Sycamore. Perhaps most significant, Willow was fabricated at Google’s new state-of-the-wafer fab facility in Santa Barbara, California. Previously, the Sycamore chip was fabricated at a facility at the University of California Santa Barbara (UCSB). The company also implemented design improvements in the chip design that provided a five-fold improvement in T1 coherence time, from 20 microseconds to 100 microseconds, an improvement in gate fidelity by roughly a factor of two, and, an increase in the number of qubits from 72 to 105.
In their technical paper published in Nature, they report an implementation of the surface error correction code with grids of 3×3, 5×5, and 7×7. Significantly, as they increased the code size they saw an improvement of roughly a factor of two in logical error rate performance as shown in the chart below.
Although achieving a logical error rate of about 10-3 is pretty good, when one looks at where Google is on their roadmap as shown below, they still have a long way to go. Now that they have a logical qubit with an error rate of 10-3 using 105 qubits, their next goal is to achieve Milestone 3 and demonstrate a logical qubit error rate of 10-6. If the Google team were to continue to scale up the existing qubit design to larger grid sizes and also continue the improvement rate as shown in the graph above, they would require 1457 physical qubits in order to reach this 10-6 logical error rate specified in the Milestone 3. But it is probably more likely that the team will continue making additional improvements either in the hardware design or the error correction code so they can be more efficient in achieving this Milestone 3 goal. Another important step in creating a fault tolerant quantum computer will be to show that they can implement a universal gate set by demonstrating gate operations including a non-Clifford gate such as the T-gate.
For more details you can view two blogs posted on the Google AI website here and here, two videos that discuss the experiment and the implications here and here, and the Nature article available here.
December 9, 2024
