A group consisting of Hewlett Packard Enterprise (HPE), Qolab, Applied Materials, 1QBit, Synopsis, Quantum Machines, and others have published a document that describes what they see as the technical challenges that need to be overcome to develop a useful Fault Tolerant Quantum Computer (FTQC) based upon superconducting technology. In this research, the hardware design was provided by Qolab, the software design by HPE, software scaling and real-time error correction designs were made by HPE, 1QBit, and Quantum Machines, and design simulations performed by Qolab, Applied, Materials. The intent is to publish something that enumerates the technical challenges so that the many organizations can come together and collaborate to accelerate the achievement of a working design.
The approach the group proposes would use system engineering approaches, existing semiconductor processing to build high quality, uniform qubits and reduce manufacturing costs, and utilize distributed quantum computation within a high-performance computing infrastructure.
The propose design would contain up to 20,000 qubits per chip in a process that would include wafer scale integration to distribute the wiring. The design would including adjustable couplers and have a gate fidelity target of about 10-4, about an order of magnitude better than what the best superconducting devices are achieving today. The proposed FTQC code is a rotated surface code since the chip would have a 2D topology and nearest-neighbor interactions. Gate times would be on the order of 25 nanoseconds and T1 coherence in the range between 200 and 340 microseconds. The design would include a low power qubit readout that uses a Josephson photomultiplier circuit which eliminates the need for large circulators and parametric amplifiers.
The design would be expected to use cryogenic control to reduce power consumption, system size, and signal stability. Real time error decoding would be implemented using NVIDIA’s DGX Quantum system. The paper also includes resource estimates that provide physical qubit and runtime estimates for a few different algorithms under different performance scenarios using both 1QBits’ TopQAD tool and Microsoft’s Azure Quantum Resource Estimator (QRE) tool. The design would be intended to be used in a hybrid quantum-classical HPC stack and would work with software stacks such as the HPE Cray Programming Environment (CPE). Programming the computer would likely be supported by existing Software Development Kits (SDKs) such as CUDA-Q, Qiskit, Cirq, Pennylane, Classiq, and possibly others.
You can access the full document posted on arXiv here. Also, a blog introducing the paper has been posted on the HPE website and can be seen here.
November 18, 2024
