IBM (NYSE: IBM) has been selected to advance to Stage C of the Quantum Benchmarking Initiative (QBI), a program overseen by the Defense Advanced Research Projects Agency (DARPA). The selection moves IBM into the independent verification and validation (IV&V) evaluation phase, where DARPA technical teams perform physical testing and measurement of IBM’s quantum hardware, cryogenic systems engineering, software stack, and fault-tolerant processor architectures.
Launched by DARPA in 2024, the QBI framework was established to rigorously evaluate whether commercial quantum hardware architectures can deliver utility-scale fault-tolerant quantum computing (FTQC) by 2033—defined as systems where the computational value created exceeds total capital and operational expenditures. Having completed Stage A (technical concept analysis) and Stage B (comprehensive R&D blueprint and risk-mitigation review), IBM’s transition to Stage C shifts the assessment from theoretical modeling to empirical hardware validation.
1. DARPA Quantum Benchmarking Initiative (QBI) Progression Stages
The QBI evaluation framework uses a multi-tier verification process to audit commercial FTQC roadmaps:
| [ DARPA Quantum Benchmarking Initiative (QBI) Stage Architecture ] | ||
|---|---|---|
| QBI Program Stage | Assessment Criteria & Verification Scope | IBM Execution Status |
| • Stage A | • Initial technical concept submission • Plausible near-term path to cost-effective FTQC | • Completed (Selected in initial cohort) |
| • Stage B | • Comprehensive R&D execution blueprint • Detailed risk assessment & technical mitigation modeling | • Completed (Audited in 2025 cohort) |
| • Stage C | • Empirical hardware testing by DARPA IV&V teams • Benchmarking of physical QPUs, cryogenics, and QEC decoders | • Active (Selected October 2026) |
2. IBM Fault-Tolerant Hardware Roadmap & Starling Benchmarks
IBM’s Stage C verification centers on its technological trajectory toward delivering IBM Quantum Starling, its target FTQC system scheduled for 2029. Key technical milestones underpinning this roadmap include:
- System Performance Target: Starling is engineered to execute 100 million quantum gate operations across 200 logical qubits at its Poughkeepsie, NY facility, leveraging low-overhead quantum error correction (QEC) codes.
- Modular Cryogenic Architecture: Integration of short meter-scale quantum interconnects and multi-cell cryostats operating below 15 millikelvin, designed to cool and control at least 2,000 physical qubits per modular cell.
- Decoder Efficiency & Qiskit Stack: Hardware-level QEC advances, including real-time error-correction decoding executed on FPGA co-processors alongside compiler optimizations within the Qiskit software suite.
Review the full announcement via the IBM Newsroom here and read our previous coverage on IBM’s 2029 Starling modular cryogenic architecture here and DARPA’s Quantum Benchmarking Initiative cohort selection here.
October 7, 2026