A Brief Look at D-Wave’s Future Product Roadmap



At the Cambridge Wireless Tec (CWTEC) conference this week, Collin Williams, Director of Business Development and Strategic Partnerships showed the slide below with an indication of D-Wave’s roadmap.

colin-williams-cwtec-september-14-2016-cstojglwcaarb2h

From the description above, it appears that 2000 qubit system in early 2017 will be based upon the same Washington chip architecture used in the D-Wave 2X.    As shown in the picture below, the Washington chip is architected as a 16×16 array of cells with each cell containing eight qubits.   The D-Wave 2X only used a 12×12 matrix from this chip providing up to 1152 qubits.  So the next generation will likely use a revision of the Washington chip so they can utilize the full 16×16 array and achieve up to 2048 qubits.

d_wave-washington

Other improvements will provide added control over the annealing time as some researchers have reported improved results by having the capability to slow the annealing down, speeding it up, or even pausing it.  The fastest anneal time in the D-Wave 2X machine was 20 microseconds and this next generation will be able to anneal in as little as 5 microseconds.  Overall, this new machine (perhaps they will call it the D-Wave 3) will be an incremental improvement over the D-Wave 2X based upon much of the same hardware.  Still, Colin mentioned that D-Wave has seen a 1000X improvement on some problems in early testing of this machine.

The 2018 machine, apparently with codename Xler, may represent a more significant change.   One of the limitations of the current D-Wave architecture is that each qubit can only couple with six neighboring qubits.   And you can only directly couple two qubits together.   If you have a problem that requires coupling three or more qubits, you have to do it indirectly.  A user may be required to either chain or clone qubits and use multiple physical qubits to obtain a logical qubit.  These constraints on connectivity can have a significant impact on how easy and efficient it is to configure problems to run on the machine.   The 2018 machine need to use a new generation of chip architecture to show improvements in connectivity as well as provide a further increase in the number of qubits.   Overall, these improvements will allow larger problems to be run and offer additional speed improvements.

 

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