SEEQC and the National Quantum Computing Centre (NQCC), in collaboration with NVIDIA, have demonstrated a digital interface system with supercomputing hardware. The system is intended to support scalable Quantum Error Correction (QEC) for the entire ecosystem.
The system, hosted at the NQCC, meets the throughput demand of quantum computers by combining SEEQC’s digital quantum-classical interface architecture with the GPU-accelerated NVIDIA CUDA-Q platform. The digital interface system is said to achieve up to 1,000x more efficient data throughput from QPU to GPU than competing analogue systems, reducing terabits to gigabits per second without performance loss. The system is powered by SEEQC’s digital quantum computing-on-a-chip architecture, which uses Single Flux Quantum (SFQ) logic technology.
The low latency and throughput efficiency of the new interface system aims to enable real-time QEC, which is considered essential for realizing practical, scalable QEC. The co-location of quantum and HPC resources with this technology at the NQCC is positioned to help the UK in delivering quantum computers for both science and industry. This system delivery builds on SEEQC’s previously announced digital quantum–classical interface protocol demo, which was unveiled during NVIDIA Quantum Day at GTC.
Read the full announcement here.
September 19, 2025
