ZeroRISC, in collaboration with the Max Planck Institute for Security and Privacy and Academia Sinica, released a production-grade open-source cryptographic hardware and software stack. The solution combines the Cryptolib embedded library with a programmable Asymmetric Cryptography Coprocessor (ACC) designed for both classical and post-quantum operations. The release provides hardware-accelerated implementations of NIST-standardized algorithms, including ML-KEM, ML-DSA, and SLH-DSA, to secure embedded silicon against quantum-based threats.
The hardware-software co-design includes extended vector ISA instructions, specialized multiplier and adder hardware, and additional datapath registers within the ACC. These modifications resulted in a 6–9x speedup for lattice-based algorithms and a 36–75% improvement in maximum operating frequency. Software refinements, such as novel rejection sampling and memory optimizations, reduced ML-DSA stack usage by over 90% and cut cycle counts by half. The architecture is modular, allowing silicon integrators to parameterize the RTL and software library to include or exclude specific PQC hardware extensions based on area or power constraints.
This technical development originated from a multi-year collaboration between industrial engineers and academic researchers, building on peer-reviewed work presented at IEEE S&P 2025 and CHES 2026. The stack supports a full range of classical primitives, including AES, SHA2/3, RSA, and Elliptic Curve Cryptography (ECDSA, ECDH), alongside the newer post-quantum standards. The combined consortium presented the methodology behind migrating a Silicon Root of Trust to PQC at Real World Crypto 2026 in Taipei.
For technical documentation and the full optimization roadmap, consult the official ZeroRISC announcement here.
March 9, 2026
