IonQ quantum information researchers Min Ye, Andrii Maksymov, and Nicolas Delfosse have published research on arXiv (arXiv:2608.25027) detailing an end-to-end real-time Quantum Error Correction (QEC) decoding pipeline for large-scale trapped-ion quantum computers.
Executed entirely on a single off-the-shelf Apple M4 Max CPU (12 cores used), the decoding stack processed MegaQuOp-scale workloads featuring up to 408 logical qubits and over 1 million T gates / 1.3 million logical measurements with near-zero computational stretch (decoding backlog delays).
| [ IonQ MegaQuOp Real-Time QEC Decoding Stack ] | ||
|---|---|---|
| Hardware Architecture & Scale | Decoding Pipeline & DEM Strategy | Performance & Stretch Metrics |
| • Walking Cat Architecture (WCA) | • Dual Sliding-Window Decoders | • 12 Cores on Apple M4 Max CPU |
| • Up to 408 Logical Qubits (68 LDPC Blocks) | • Static Tanner Graph with On-the-Fly DEM Priors | • <0.3% Stretch at pCNOT = 10⁻⁴ (1–5 ms SEC) |
| • 20 Magic State Factories (11,680 Physical Qubits) | • Beam Search + LLR Memory Optimizations | • <12% Stretch at pCNOT = 5 × 10⁻⁴ (Worst-Case) |
Addressing the Real-Time Decoding Backlog Bottleneck
As quantum processors scale to execute millions of operations across logical qubits (a MegaQuOp), processing syndrome extraction data in real-time is necessary to prevent an exponential computational slowdown caused by decoding backlogs. While prior efforts focused on decoding individual memory blocks or small operations using specialized FPGAs, GPUs, or ASICs, IonQ demonstrated a software decoding pipeline running on a general-purpose commodity CPU:
- Dual-Decoder Architecture: The pipeline employs two sliding-window decoders operating concurrently. A continuous Error Decoder (5-cycle window) tracks Pauli frames to suppress long-term logical errors, while a low-latency Outcome Decoder (2-cycle window) launches during logical measurements to resolve Viterbi stopping conditions and error-detected measurement (EDM) checks.
- On-the-Fly Detector Error Model (DEM) Generation: Rather than rebuilding complex parity-check matrix graphs when cat-state measurements occur, the system reuses a fixed Tanner graph and updates only the probability prior vectors dynamically on the fly.
- Memory & LLR Optimizations: By storing log-likelihood ratios (LLRs) per error node rather than raw Tanner-graph edge messages, the team reduced decoder memory traffic and memory footprint by more than an order of magnitude, preventing cache contention across concurrent CPU processes.
Benchmark Workloads and Hardware Roadmap Validation
The team evaluated the real-time decoder across three large-scale fault-tolerant circuits compiled for IonQ’s Walking Cat Architecture (WCA):
- Measurement-Induced Phase Transition (MIPT): 102 logical qubits, 1.08M T gates, and 1.10M logical measurements (22 code blocks).
- Disordered Heisenberg Model (n64): 102 logical qubits, 139k T gates, and 327k logical measurements (22 code blocks).
- Disordered Heisenberg Model (n266): 408 logical qubits, 555k T gates, and 1.31M logical measurements across 88 code blocks (68 memory blocks + 20 CH2 magic state factories totaling 11,680 physical qubits).
Assuming syndrome extraction cycle (SEC) times of 1 ms to 5 ms typical for trapped-ion hardware, the decoding backlog induced an operational time delay (“stretch”) of less than 0.3% at a physical error rate of pCNOT = 10⁻⁴ across all workloads, and remained below 12% even under elevated physical noise (pCNOT = 5 × 10⁻⁴).
The results validate that classical decoding bandwidth will not act as a bottleneck for IonQ’s WCA roadmap as systems scale toward 10,000+ physical qubits.
Review the full paper on arXiv:2608.25027 here.
August 27, 2026
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