Quantum hardware developer D-Wave Quantum Inc. (NASDAQ: QBTS) has published peer-reviewed research in Nature demonstrating a fast, high-fidelity two-qubit entangling gate for superconducting dual-rail cavity qubits. Titled “An entangling gate for dual-rail erasure qubits,” the study validates a foundational milestone in D-Wave’s gate-model development strategy. Led by Chief Scientist Dr. Robert Schoelkopf, Chief Development Officer Dr. Trevor Lanting, and CEO Dr. Alan Baratz, the research addresses the physical qubit overhead of fault-tolerant quantum computing by converting dominant photon loss events into hardware-detectable erasure errors at known spacetime locations.
The experimental demonstration introduces a Swap–Wait–Swap (SWS) controlled-phase (CZ) gate executed between dual-rail cavity qubits linked via a tunable transmon coupler. Operating at a gate speed of approximately 500 nanoseconds, the SWS protocol temporarily swaps a cavity photon into the coupler to exploit strong dispersive shifts before restoring the excitation. The gate achieved an overall physical fidelity of approximately 99.9%, with an erasure rate of ∼ 0.5% per gate and post-selected residual Pauli errors below 0.1%. The architecture preserves a strong noise bias: bit-flip errors were suppressed down to the 10-6 level (parts per million), while dephasing errors dominated residual noise. Furthermore, the gate exhibits benign leakage propagation—where photon loss to the vacuum state (∣00⟩) deactivates the dispersive interaction—allowing surface-code syndrome extraction cycles to defer erasure checks to the end of a round without sacrificing code distance or triggering correlated error cascades.
[ D-Wave Gate-Model Fault-Tolerance Roadmap ]
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2026 (DR17) 2028 (DR181) 2032 (100 Logical)
• 17 Dual-Rail Physical Qubits. • 181 Dual-Rail Physical Qubits. • 100 Fault-Tolerant Logical Qubits.
• 2x Logical Error Reduction. • 2,000x Error Suppression Factor. • >1 Million Logical Operations.
• Hardware-Level Erasure Tracking. • Scalable Blueprint & Real-Time Dec. • Commercial Quantum AI & Chemistry.Surface-code numerical simulations leveraging these experimental parameters demonstrate that D-Wave’s dual-rail architecture can achieve an error reduction factor (Λ) of 10 for each increment in error correction code distance. A (Λ) value of 10 indicates that logical error rates drop by a factor of 10 with each additional error-correction layer, significantly easing physical qubit requirements compared to standard transmon or planar surface-code implementations. This hardware-level error awareness allows fault-tolerant logical qubits to be constructed with substantially lower physical qubit counts and simplified classical decoding overheads.
The breakthrough directly underpins D-Wave’s multi-year gate-model development roadmap, complementing its commercial quantum annealing platforms. The roadmap targets a 17-physical-qubit system (DR17) in 2026 delivering a 2× logical error reduction, a 49-physical-qubit system (DR49) in 2027 with a 20× reduction, and a 181-physical-qubit system (DR181) in 2028 providing a 2,000× error suppression factor as a blueprint for fault-tolerant scaling. By 2030, D-Wave plans to complete a 10-logical-qubit system for initial fault-tolerant algorithm execution, culminating in a 100-logical-qubit system by 2032 capable of executing over 1 million logical operations for quantum chemistry, materials science, and quantum AI applications. The gate-model platform will be accessible via D-Wave’s Leap™ quantum cloud service, supported by real-time quantum-classical control and the Quantum Circuit Description Language (QCDL).
Review the complete peer-reviewed study in Nature here, inspect system architecture specifications on the D-Wave Gate-Model Portal here, and read the official announcement on the D-Wave Newsroom here.
August 6, 2026
