Silicon quantum hardware developer Quobly and microelectronics research institute CEA-Leti have expanded their joint technology program, securing Quobly direct access to the European FAMES Pilot Line (FD-SOI Pilot Line for Applications with embedded non-volatile Memories, RF, 3D Integration & PMIC). Hosted at CEA-Leti in Grenoble under the Chips JU initiative, the pilot line complements Quobly’s commercial manufacturing partnership with STMicroelectronics, providing advanced processing tools to prototype 3D integration, radio-frequency (RF) control layers, and process flows for next-generation quantum processing units (QPUs).
Quobly’s architecture, QSOI®, integrates silicon spin qubits directly onto a 300 mm fully depleted silicon-on-insulator (FD-SOI) CMOS substrate. The platform combines spin-qubit arrays with cryogenic control electronics on a unified die, leveraging Very Large-Scale Integration (VLSI) manufacturing principles. By leveraging the FAMES infrastructure’s 3D integration and embedded non-volatile memory capabilities, Quobly aims to scale qubit density and pulse-control performance on standard 300 mm foundry lines without expanding thermal or physical footprints.
| [ Quobly & CEA-Leti Technical Integration & Roadmap Architecture ] | ||
|---|---|---|
| Partner Entity | Functional Capability | Strategic Contribution to QSOI® Roadmap |
| • CEA-Leti & FAMES Pilot Line | • Microelectronics RTO & Chips JU Pilot Line • FD-SOI, RF, 3D Integration, & eNVM | • Process flow experimentation, lithographic patterning, 3D integration, and yield optimization |
| • STMicroelectronics | • Industrial 300 mm Semiconductor Foundry | • High-volume QPU fabrication on commercial 300 mm FD-SOI production lines |
| • Air Liquide, Soitec, Orano | • Specialized Substrate & Gas Supply Chain | • Securing isotopically purified Silicon-28 ($^{28}\text{Si}$) substrate materials |
Access to FAMES establishes an intermediate prototyping bridge between exploratory R&D and commercial foundry runs at STMicroelectronics. Quobly plans to offer initial cloud availability for its first-generation processor family, Alloy Pioneer, by late 2026, targeting a long-term scaling trajectory toward large-scale, fault-tolerant silicon architectures by 2032.
Review the technical press release via Quobly Press Releases here and inspect European pilot line capabilities on the FAMES Pilot Line Portal here.
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