SEALSQ Corp (NASDAQ: LAES) has unveiled the Quantum Shield QS7001, a new secure chip that integrates NIST-standardized Post-Quantum Cryptography (PQC) algorithms directly at the hardware level. The chip was debuted at the IQT Quantum+AI 2025 Conference in New York City and is scheduled for its official launch in mid-November 2025.
The QS7001 is built on a 32-bit Secured RISC-V Architecture Microcontroller and integrates ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) algorithms. Key features include a dedicated hardware cryptographic accelerator, 512K Bytes of FLASH memory, and support for communication interfaces up to 33MBits/s. This native hardware implementation is intended to provide up to 10x performance gains and enhanced security against side-channel attacks and physical tampering. The chip is targeting Common Criteria EAL5+ and FIPS SP800-90B certification.
This launch is positioned as a direct response to global mandates for PQC adoption, including the U.S. CNSA 2.0 framework and upcoming EU regulations. The chip is intended to provide a native hardware foundation for quantum-safe security across critical sectors such as defense, healthcare, energy, and connected IoT devices. SEALSQ also plans to release QVault TPM variants starting in the first half of 2026.
Carlos Moreira, CEO of SEALSQ, noted that by embedding PQC directly in hardware, the chip is intended to provide a robust foundation for long-term security in high-stakes environments. Commercial development kits for the QS7001 will be available for purchase in November 2025.
Read the full announcement here, the early launch details here, and the official QS7001 Summary Datasheet here.
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