Publicly traded photonic quantum computing developer Xanadu Quantum Technologies (NASDAQ/TSX: XNDU) and semiconductor lithography leader ASML (NASDAQ: ASML) have entered into a research collaboration to advance lithographic process nodes for photonic quantum hardware. The joint technical program targets the reduction of optical propagation losses within integrated silicon photonic circuits—a primary physical barrier to achieving fault-tolerant quantum error correction in light-based QPUs.
The technical engagement focuses on mitigating Line Edge Roughness (LER), a nanometer-scale sidewall imperfection introduced during deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) photolithography and etch processing. In photonic quantum networks, LER induces Rayleigh scattering, causing photons to scatter out of integrated optical waveguides. By leveraging ASML’s advanced exposure systems and computational lithography, the partnership aims to establish optimized patterning conditions to achieve ultra-smooth waveguide sidewalls, minimizing photon loss across complex routing circuits and squeeze-state generation modules.
Reducing optical loss directly lowers the physical qubit overhead and photon-subtraction thresholds required for quantum error correction in room-temperature photonic architectures. The collaboration marks an expansion of Xanadu’s semiconductor ecosystem footprint, supporting its manufacturing transition toward commercial-scale photonic chips engineered for utility-scale fault tolerance.
Review the official press release on GlobeNewswire here and examine our previous coverage of Xanadu’s Fault-Tolerant Photonic Hardware Roadmap here.
September 9, 2026
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