European energy utility E.ON, quantum software developer Qoro Quantum, and the UK National Quantum Computing Centre (NQCC) have demonstrated a distributed hybrid optimization pipeline that cuts quantum execution time on IBM Quantum hardware by approximately 3×. The investigation, detailed in a preprint titled Scaling Quantum Optimization to the Thousand-Qubit Scale with Distributed Quantum Sampling, focuses on the Minimum Birkhoff Decomposition (MBD)—an NP-hard problem central to network scheduling, optical routing, and decentralized peer-to-peer (P2P) energy trading. Conducted under the UK SparQ program with technical oversight from the STFC Hartree Centre, the team mapped the 1,354-bus, 1,710-line PEGASE-1354 European transmission grid benchmark onto commercial 156-qubit IBM Heron processors by decomposing a native 1,710-variable problem into 41 subgraphs bounded to ≤ 50 qubits each.
Algorithmic Core: Extended Frank-Wolfe, Spectral Partitioning, and Greedy Feasibility Repair
The MBD seeks to reconstruct general network demand matrices as sparse linear combinations of valid matchings (subgraphs where no two edges share a vertex). The collaboration integrated shallow, single-layer (p = 1) Quantum Approximate Optimization Algorithm (QAOA) sampling into an Extended Fully-Corrective Frank-Wolfe (E-FCFW) framework. To bypass continuous parameter tuning loops during runtime, the team pre-calibrated fixed variational angles offline: (γ0, β0) ≈ (2.49, 0.16) for the transmission network. Multi-way spectral graph partitioning divided the residual demand graph into subproblems bounded by edge count (qubit width) ps ≤ 50. Output bitstrings from independent subproblems were stitched using batched Cartesian products, followed by an O(|E| log |E|) classical greedy repair routine that sorts candidate edges by residual weight and discards conflicting edges sharing common vertices, strictly preserving physical matching feasibility.
| Distributed Quantum MBD Optimization Benchmarks on PEGASE-1354 | ||
|---|---|---|
| Workflow Metric / Dimension | Demonstrated Value / Configuration | Algorithmic & Operational Significance |
| Target Grid Benchmark | PEGASE-1354 (1,354 Buses, 1,710 Lines) | Industrial European high-voltage transmission benchmark with 1,710 edge variables. |
| Unpartitioned Qubit Footprint | 1,710 Qubits | Full line-graph formulation requiring edge-to-qubit mapping exceeds single QPU capacities. |
| Distributed Subgraphs | 41 Partitions (Bound ps ≤ 50 Qubits) | Multi-way spectral partitioning preserves local interaction density while isolating cut edges. |
| Hardware Execution Engine | IBM Heron (ibm_marrakesh & ibm_kingston) | Spatial packing maps four independent circuits (144 qubits total) onto a 156-qubit QPU. |
| Throughput & Runtime Factor | ≈ 3× Measured Execution Speedup | Concurrent execution across disjoint lattice zones reduces QPU submission rounds by up to 4×. |
| Residual Decomposition Error | 1.11 × 10−6 (Unpacked) / 1.58 × 10−6 (Packed) | Outperforms classical simulated annealing and uniform random sampling under identical greedy repair. |
Entanglement Truncation Diagnostics and Near-Term Scaling Constraints
The researchers investigated whether distributed partitions preserve meaningful quantum advantage or merely mimic classical heuristics. In matrix product state (MPS) simulations conducted via Qoro’s Maestro engine, truncating quantum correlations across low bond dimensions (χ ≤ 16) led to degraded candidate quality and higher residual errors, whereas higher bond dimensions (χ = 128) closely tracked hardware convergence. Aggressive partitioning down to 20 qubits degraded solution convergence because too many inter-partition edges were severed, whereas 50- and 80-qubit partitions maintained convergence near unpartitioned baselines. However, the study revealed that circuit width alone does not govern execution difficulty: due to line-graph connectivity, tightly clustered degree-3 junctions require dense SWAP routing, driving transpiled two-qubit depths up to 169 even on 50-qubit subgraphs. Hardware runs omitted active pulse-level dynamical decoupling and gate twirling because the added circuit latency increased decoherence, relying instead on depth-minimized transpilation coupled with classical post-repair.
The peer-reviewed methodology and technical benchmarks are detailed in the preprint on arXiv here.
October 29, 2026
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