In a research paper published on arXiv, researchers Ahmed Adel Mahmoud and Dr. Steven Rayan from the Centre for Quantum Topology and Its Applications (quanTA) at the University of Saskatchewan have demonstrated explicit finite families of geometry-optimized hyperbolic surface codes that attain the optimal efficiency scaling limit set by Delfosse’s bound (η = kd2/n ∝ (log k)2).
By optimizing the periodic boundary conditions of higher-genus hyperbolic manifolds, the authors show that code distance can be doubled, quadrupling overall code efficiency, without increasing physical qubit count, encoding rate, or local parity-check weight. Conventional 2D Euclidean surface codes are constrained by the Bravyi–Poulin–Terhal (BPT) bound, which limits code efficiency to η = kd2/n = O(1). By embedding quantum low-density parity-check (qLDPC) interactions onto compactified hyperbolic surfaces, the researchers executed an exhaustive algebraic search across self-dual {p, p} tessellations for p in {5, 6, 7, 8}.
Among the discovered families, the optimal {6, 6} code [[51330, 17112, 10]] encodes 17,112 logical qubits into 51,330 physical qubits and achieves a record code efficiency of η ≈ 33.34. This represents a 33-fold efficiency improvement over the standard 2D toric code and a 6.6-fold gain over reported hyperbolic Floquet code benchmarks. Other high-efficiency instances include a {5, 5} code [[51330, 10268, 12]] achieving η ≈ 28.81 with 10,268 logical qubits, a {7, 7} code [[17220, 7382, 8]] achieving η ≈ 27.44 with 7,382 logical qubits, and an {8, 8} code [[25944, 12974, 8]] achieving η ≈ 32.00 with 12,974 logical qubits.
To bridge non-Euclidean hyperbolic geometry with physical hardware constraints, the authors developed a topology-aware compiler that partitions large-scale hyperbolic codes into planar modules featuring a strict capacity upper bound of 80 or fewer qubits per chip. Using Stim and PyMatching under an SI1000-like circuit noise model, memory experiments across homological distances d in {6, 8, 10, 12} yielded an error-correction threshold of approximately 0.22% for uniform physical gate errors (α = 1). When the error probability of long-range inter-module CNOT gates was tripled (α = 3), the threshold experienced only mild degradation, holding at approximately 0.17% for modular layouts and 0.18% for monolithic layouts.
| [ Key Quantum Error Correction Parameters ] | ||
|---|---|---|
| Parameter | Name | Definition & Operational Meaning |
| • n | • Physical Qubits | • The total count of raw, physical hardware qubits built onto the quantum processing chip. |
| • k | • Logical Qubits | • The number of error-protected, reliable qubits created by bundling physical qubits together to perform calculations. |
| • d | • Code Distance | • The minimum number of physical error events needed to corrupt a logical qubit. A larger distance allows the system to detect and correct more errors. |
| • η = kd2/n | • Code Efficiency | • The ratio measuring how many logical qubits (k) and how much protection (d) are achieved relative to the physical qubit budget (n). Higher values represent greater hardware efficiency. |
What This Discovery Means in Plain English
Think of physical qubits as fragile glass ornaments and quantum noise as accidental bumps during shipping. Standard quantum error correction protects one fragile ornament by packing it inside a large box filled with dozens of plain foam packing peanuts (physical qubits). While this works, it requires an overwhelming amount of foam to protect just a few items, making large quantum computers extremely expensive to build.
The University of Saskatchewan researchers solved this overhead problem by designing a new “packing box” shaped like a multi-dimensional, curved hyperbolic geometric surface. Instead of wrapping one ornament at a time, this unique geometric layout wraps thousands of fragile ornaments together using shared, highly organized foam connections.
Furthermore, the researchers created a smart compiler that lets hardware engineers chop this curved pattern into tiny, flat 80-qubit microchips while preserving the protective wrap. As a result, future quantum computers will be able to run thousands of protected logical operations using a fraction of the physical hardware previously required, bringing practical, fault-tolerant quantum supercomputing much closer to reality.
Review the full pre-print research paper on arXiv here and read author insights in Ahmed Adel Mahmoud’s post here.
In GQI Portal
The players behind the news
The team that writes QCR tracks every company, deal and technology in the GQI Factory, GQI's verified database of the quantum industry. Next up: every story linked to its players, coming to QCR's paid plans.
- Players Companies and institutions across the quantum industry, by segment.
- Scorecards How the players compare on hardware, software, funding and more.
Newsletter
QCR Alerts in your inbox
The latest reporting and analysis from Quantum Computing Report. Free, unsubscribe any time.