Mohamed Abdel-Kareem

QuantWare and Maybell Quantum have entered a strategic partnership to ensure hardware compatibility between Maybell's ColdCloud cooling infrastructure and QuantWare's upcoming VIO-40K superconducting quantum processing units (QPUs). By co-designing the processor layout alongside the underlying cryogenic framework, the collaboration aims to optimize the compute-per-watt performance of hyperscale quantum computers. The open-architecture alignment prepares the hardware supply chain for data-center deployments as QuantWare plans to deliver 10,000-qubit processors by 2028. [ Centralized 4K Pre-Cooling Plant ] ──► [ Decoupled Independent Nodes (<10 mK) ] ──► QuantWare VIO-40K QPU (10,000 Qubits) Monolithic Chiplet Scaling and Silicon-Based QPU Density QuantWare’s VIO QPU architecture is [...]

QuEra Computing Inc. has released its updated product roadmap during a strategic webinar briefing, detailing the transition timelines from Noisy Intermediate-Scale Quantum (NISQ) systems to error-corrected hardware classes. The revised roadmap—anchored upon peer-reviewed academic foundations—outlines a development path optimized for a modular, zoned neutral-atom hardware infrastructure. By substituting fixed qubit layouts with parallel atom-shuttling connectivity, the company targets the execution of multi-variable fault-tolerant algorithms by 2028, bypassing standard cryogenic cooling footprint mandates through room-temperature vacuum cell operations. [ Aquila (2022) ] ──► [ Gemini (2025) ] ──► [ Libra (2028) ] ──► [ Next Gen (2028+) ] Static NISQ QEC Testbed [...]

Faculty Scientist Dan Stamper-Kurn adjusts the optics on a laser experiment. (Credit: Thor Swift/Berkeley Lab) Lawrence Berkeley National Laboratory (Berkeley Lab) has reported the status of its quantum industry collaborations, focusing on the integration of commercial systems and public research infrastructure. Through the National Energy Research Scientific Computing Center (NERSC), the Quantum Computing Access program provides researchers with access to quantum processors from QuEra Computing Inc. and IBM. This layout permits the high-performance computing user base at NERSC to run operations in quantum simulation, chemistry, materials science, and condensed matter physics, utilizing QuEra’s neutral-atom platform, Aquila, and its internal magneto-optical trap array [...]

The architecture for the DX, DZ decoder. Memory elements shown in blue (light for RAM, dark for ROM). I/O in purple. Sub-modules in gray. Researchers from the IMDEA Software Institute, Nokia Bell Labs, the Complutense University of Madrid, Aalto University, and Quobly have developed an FPGA-based hardware architecture for the real-time decoding of quantum LDPC codes. Published on ArXiv, the design manages correlated error arrays within a structural layout optimized for latency, physical area, and power consumption. The architecture utilizes targeted resource reuse loops rather than unrestricted hardware parallelization to process complex multi-qubit syndromic dependencies, addressing classical computational processing bottlenecks that [...]

Overview of transversal STAR architecture. QuEra Computing and Los Alamos National Laboratory have introduced a co-designed quantum computing architecture named transversal STAR (Space-Time Efficient Analog Rotation). Published in PRX Quantum, the framework reduces the physical qubit overhead and gate-synthesis clock cycles required for early fault-tolerant quantum simulation. Designed specifically for neutral-atom hardware arrays, the architecture optimizes calculations in materials science, condensed matter physics, and non-equilibrium many-body dynamics, moving execution speeds closer to the "megaquop" regime—the milestone where an error-corrected system completes one million reliable logical operations. [ Standard FT ] Small-Angle Rotation ──► Magic State Distillation ──► Solovay-Kitaev Synthesis (High Overhead) [...]

Semiconductor manufacturer STMicroelectronics has introduced the ST54M, a single-die secure mobile processor equipped with a hardware accelerator for Post-Quantum Cryptography (PQC). Designed for smartphones and personal electronics, the chip integrates Near Field Communication (NFC) control circuits, a secure element, and embedded SIM (eSIM) functionality on a single substrate. The hardware platform targets upcoming security standards scheduled for industry-wide adoption around 2030, enabling mobile device makers to deploy quantum-resistant encryption parameters across connected consumer and enterprise services. [ Embedded SIM (eSIM) ] │ [ NFC Controller ] ──► [ ST54M Single Die ] ──► [ Hardware PQC Engine ] ──► ML-KEM / [...]

Software developer Classiq and innovation center Hatch have completed a computational chemistry proof-of-concept (PoC) to estimate molecular binding energy via Amazon Web Services (AWS) and Amazon Braket. Executed through Hatch’s Dimension X open innovation challenge for Singapore’s Home Team and aligned with Singapore’s National Quantum Strategy, the project establishes a functional pipeline for analyzing how small molecules interact with protein target structures. By pairing AWS high-performance classical computing nodes with Classiq's quantum software platform, the workflow demonstrates an enterprise model for calculating molecular recognition indicators before committing to laboratory testing. Wavefunction-in-DFT Orbit Embedding and Active Space Selection Calculating molecular binding energy [...]

Classiq and technology company TEA TEK Group have announced a strategic partnership to establish a quantum computing hub in Naples, Italy. The facility is configured to operate as a center for quantum computing research, software compilation, and commercial services within Italy and the European Union. By connecting a 128-qubit quantum hardware system with Classiq’s algorithm design platform, the hub will supply a unified workflow allowing academic researchers, public institutions, and industrial enterprises to build and execute quantum applications. The infrastructure deployment replicates the technical framework utilized by the Quantum Computing Napoli (QCN) Lab at the University of Naples Federico II (UNINA), [...]

The Jülich Supercomputing Centre (JSC) has established an operational baseline in classical quantum emulations by executing a full simulation of a universal 50-qubit quantum computer. Conducted on JUPITER, Europe’s initial exascale supercomputer hosted at Forschungszentrum Jülich in Germany, the achievement utilizes the JUQCS-50 (Jülich Quantum Computer Simulator) framework developed alongside the jointly run NVIDIA Application Lab. By scaling the emulation threshold to 50 qubits, the project surpasses the previous classical simulation record of 48 qubits, providing a high-fidelity verification baseline that physical quantum hardware must outpace to demonstrate computational quantum supremacy. [ Quantum State Vectors ] ──► Exponential Scaling O(2ⁿ) ──► [...]

Bull and quantum hardware developer Alice & Bob have signed a Memorandum of Understanding to integrate quantum computing systems within high-performance computing (HPC) infrastructures. The initiative aims to connect quantum architectures with computing infrastructures to operate as co-processors. By combining Bull's system integration and manufacturing capabilities with Alice & Bob’s superconducting qubit technology, the collaboration addresses the physical and structural requirements for large-scale quantum (LSQ) hybrid acceleration. At the core of the technical alliance is Alice & Bob’s cat qubit architecture, a superconducting qubit design engineered to suppress bit-flip errors. By managing bit-flips at the hardware level via autonomous quantum stabilization, [...]