Hardware and supercomputing leaders IBM (NYSE: IBM), the Quantum Science Center (QSC) at Oak Ridge National Laboratory (ORNL), and AMD (NASDAQ: AMD) have launched a dedicated quantum error correction (QEC) co-design platform at IBM’s facility in Poughkeepsie, New York. Designed to eliminate network latency bottlenecks between heterogeneous compute tiers, the deployment co-locates IBM’s latest 120-qubit Quantum Nighthawk r2 processor with ORNL’s Umbra high-performance computing (HPC) system, powered by AMD Instinct MI355X accelerators and 5th Gen AMD EPYC CPUs.
| IBM / ORNL / AMD QEC Co-Design Platform Specifications | ||
|---|---|---|
| Architecture Pillar | Hardware & Infrastructure Profile | Technical & Operational Function |
| Quantum Compute Tier | IBM Quantum Nighthawk r2 | 120 programmable qubits in a square lattice with dynamic mid-circuit measurement and fast reset. |
| Classical Accelerator Tier | ORNL Umbra HPC System | AMD Instinct MI355X GPUs and 5th Gen AMD EPYC CPUs providing hardware-level decoding acceleration. |
| Interconnect Architecture | On-premises co-location (Poughkeepsie) | Enables sub-millisecond round-trip feedback loops required for real-time syndrome processing. |
| National Mission Alignment | DOE Quantum Genesis Mission (Q Competition) | Targets scaling from 70 logical qubits (438 operations) to 100 logical qubits across 100,000 operations by 2028. |
Fault-tolerant quantum computing requires continuous syndrome-extraction cycles where classical decoding engines process error signals fast enough to prevent physical noise accumulation from overwhelming the logical register. In traditional cloud workflows, transferring syndrome telemetry across public networks introduces transmission delays that preclude real-time conditional branching. By physically placing the Umbra cluster adjacent to the dilution refrigerator infrastructure in Poughkeepsie, the consortium establishes a high-throughput, low-latency datapath, enabling GPU-accelerated decoders to execute in step with the QPU’s 100,000 circuits-per-second repetition rates.
The co-design testbed focuses on scaling multi-layered and hierarchical error-correcting codes, where an inner topological code protects localized physical clusters while an outer code mitigates correlated spatial errors across modules. On the classical side, the platform leverages the AMD ROCm open software ecosystem alongside AMD Versal adaptive SoCs to pipeline syndrome readout directly into GPU memory. Early scientific targets center on condensed matter physics and neutron scattering analysis—matching quantum time-evolution simulations with empirical data generated by ORNL’s Spallation Neutron Source to model frustrated magnetic materials.
The testbed establishes the integrated compute foundation informing IBM’s roadmap toward its modular fault-tolerant system, IBM Quantum Starling, planned for 2029, while connecting to ORNL’s Oak Ridge Leadership Computing Facility (OLCF). Technical workflows are detailed in the IBM Official News Release here, architectural context is outlined in the IBM Quantum Research Blog here, and hardware integration strategies are available via the AMD Corporate Announcement here; related QCR reporting on Nighthawk deployments includes our coverage of Yonsei University bringing IBM Quantum Nighthawk r2 online in South Korea here.
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