A joint research collaboration between the University of Sydney Nano Institute and IBM Quantum has identified, isolated, and mitigated a major hardware engineering bottleneck hindering Fault-Tolerant Quantum Computing (FTQC). Published in Nature Communications by lead author Dr. Robin Harper and project lead Professor Stephen Bartlett, the study provides the first comprehensive quantitative benchmark of errors introduced directly by mid-circuit measurements (MCMs). The international project—co-funded by the U.S. government’s Intelligence Advanced Research Projects Activity (IARPA)—demonstrates an architectural workaround that dramatically suppresses localized noise, establishing a clearer pathway toward scalable quantum error correction (QEC).
[ MCM Circuit Optimization Metrics ]
Hardware Fabric ──► IBM Quantum Heron r2 superconducting processor (156-qubit system).
Legacy Performance ──► Idling noise during MCM feedback loops dropped logical survival below 90%.
Optimized Pipeline ──► Circuit redesign minimizes gate idling, pushing logical survival past 96%.
Quantum error correction requires a subset of physical qubits (ancilla qubits) to repeatedly audit and check the data-carrying qubits for phase and bit-flip errors without destroying the underlying superposition. This diagnostic step relies entirely on mid-circuit measurements, where specific qubits are intentionally collapsed to classical states at intermediate stages of a calculation to provide real-time error-telemetry feedback. However, because physical qubits are exceptionally fragile, the time required to complete an MCM forces all adjacent, non-measured qubits to enter an “idling” state. During this hardware delay, the idling qubits remain highly susceptible to environmental thermal noise and phase decoherence, meaning the very act of checking for errors historically introduced an accumulation of new physical faults.
To isolate this mechanism, the Sydney and IBM teams ran validation benchmarks on a physical 156-qubit IBM Quantum Heron r2 superconducting processor hosted inside an IBM Quantum System Two infrastructure. Their diagnostic data proved that measurement-induced idling noise is currently one of the primary physical limitations degrading logical gate fidelity on modern superconducting backends. To overcome this limitation, the researchers—including IBM quantum scientist Dr. Ben Brown and University College London (UCL) researcher Constance Lainé—redesigned the physical layout of the error-correction circuitry. By compacting the execution schedules to minimize the chronological time data qubits spend idling during ancilla readouts, the team successfully elevated logical qubit survival rates from below 90% up to more than 96% per individual error-correction cycle.
The official institutional research briefing, administrative project disclosures, and global talent exchange metrics can be reviewed through the University of Sydney News Portal here. The peer-reviewed physical findings, open-access datasets, and error-corrected gate failure benchmarks can be audited directly via Nature Communications here, while complementary hardware analysis can be accessed via HPCwire here.
July 4, 2026
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