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Microsoft and Quantinuum Publish Peer-Reviewed Quantum Error Correction Data in Nature

2026-06-12T11:57:54-07:00

Microsoft and trapped-ion hardware developer Quantinuum have published a peer-reviewed paper in the journal Nature detailing physical implementations of quantum error correction (QEC). The paper, titled “Improved quantum processor logical error rates via correction and detection,” presents experimental data collected using Microsoft’s qubit-virtualization platform executed on Quantinuum’s trapped-ion Quantum Charge-Coupled Device (QCCD) hardware architecture. The study documents logical error-rate reductions ranging from 11x to 800x compared to corresponding physical qubit circuit baselines, establishing experimental parameters for error suppression in non-trivial quantum circuits. Dual Code Configurations and QCCD Hardware-Aware Syndrome Extraction The technical framework utilized in the experiments combines two distinct QEC [...]

Microsoft and Quantinuum Publish Peer-Reviewed Quantum Error Correction Data in Nature2026-06-12T11:57:54-07:00

Arkeon Technologies Secures 6.5 million SEK ($691K USD) Seed Round to Commercialize Post-Fabrication Quantum Chip Trimming

2026-06-12T08:46:48-07:00

Swedish DeepTech startup Arkeon Technologies has closed a 6.5 million SEK (€594.2k) ($691K USD) Seed funding round to advance its proprietary post-fabrication precision engineering solutions for the superconducting quantum computing sector. The investment round was backed by a coalition of institutional tech investors, including Chalmers Ventures, Navigare Ventures, and Almi Invest. Founded in 2025 by Peter Hörstedt, Andreas Nylander, and Marcus Rommel, the Gothenburg-based company intends to deploy the capital to accelerate international customer validation, expand its deployment pipeline, and refine its chip-tuning methodologies for commercial foundries. Mitigating Micro-Fabrication Drift via Automated Pulse-Train Trimming A critical barrier in scaling monolithic superconducting [...]

Arkeon Technologies Secures 6.5 million SEK ($691K USD) Seed Round to Commercialize Post-Fabrication Quantum Chip Trimming2026-06-12T08:46:48-07:00

HKU Engineering Develops World-First Cryogenic Neuromorphic Chip to Advance Quantum Scaling

2026-06-12T08:22:15-07:00

Solid-state electronics researchers from the University of Hong Kong’s (HKU) Department of Electrical and Computer Engineering, working alongside the Centre for Advanced Semiconductors and Integrated Circuits (CASIC), have achieved a significant material physics breakthrough in cryogenic electronics. Led by Professor Yuhao Zhang and PhD student Xin Yang, the team has engineered a programmable, brain-like neuromorphic hardware platform that operates near absolute zero (10 mK). Published in Nature Communications, the study demonstrates how the intrinsic atomic properties of industry-standard Silicon Carbide (SiC) power transistors can be harnessed to construct energy-efficient, local data processing networks inside quantum dilution refrigerators. This milestone introduces a practical [...]

HKU Engineering Develops World-First Cryogenic Neuromorphic Chip to Advance Quantum Scaling2026-06-12T08:22:15-07:00

ORCA Computing Integrates Photonic Systems into London Digital Realty Innovation Lab

2026-06-11T21:54:10-07:00

Full-stack quantum hardware developer ORCA Computing has announced its active participation in the newly launched Digital Realty Innovation Lab (DRIL) in London, a next-generation testing environment engineered by Digital Realty, the world’s largest cloud- and carrier-neutral data center provider. The newly established facility allows enterprise customers and technology developers across the EMEA region to benchmark emerging artificial intelligence and quantum acceleration platforms under live, co-located operational conditions before executing full-scale commercial deployments. By establishing this active infrastructure node in London, the partnership provides organizations with a secure, low-risk foundry to validate hybrid classical-quantum orchestration layers within standard high-performance computing (HPC) data [...]

ORCA Computing Integrates Photonic Systems into London Digital Realty Innovation Lab2026-06-11T21:54:10-07:00

JIJ and ORCA Computing Demonstrate Hybrid Quantum-Classical Energy Optimization

2026-06-11T22:03:20-07:00

Quantum optimization software provider JIJ Inc. and photonic hardware developer ORCA Computing, in a joint corporate project with energy conglomerate bp, and the UK National Quantum Computing Centre (NQCC), have released a comprehensive benchmarking white paper validating a hybrid quantum-classical workflow tailored for the energy sector. The industrial study focuses on deploying co-processed optimization routines to solve the Unit Commitment Problem (UCP)—the large-scale computational challenge of scheduling power generator configurations to meet grid demands at the lowest possible economic and environmental cost. Numerical simulations and physical hardware execution indicate that hybrid quantum-classical decomposition models can efficiently scale to manage large-scale grid variables, [...]

JIJ and ORCA Computing Demonstrate Hybrid Quantum-Classical Energy Optimization2026-06-11T22:03:20-07:00

IQM Radiance 54 Superconducting Quantum Computer Goes Live at CINECA in Italy

2026-06-11T21:17:20-07:00

Sovereign hardware developer IQM Quantum Computers, alongside the Italian Research Centre on High Performance Computing, Big Data, and Quantum Computing (ICSC), has announced the official inauguration of the IQM Radiance 54 quantum computer at the CINECA supercomputing facility. Located at the DAMA Tecnopolo in Bologna, the system represents a strategic technology asset engineered to accelerate regional research across complex combinatorial optimization, physical simulations, and quantum machine learning. The deployment deepens Italy's sovereign computing capacity, marking the first on-premises superconducting quantum platform to go live at CINECA and the second IQM hardware system to become operational nationwide. The NOX QPU Architecture and [...]

IQM Radiance 54 Superconducting Quantum Computer Goes Live at CINECA in Italy2026-06-11T21:17:20-07:00

BW Digital and NUS CDE Launch Joint Framework for Tropical Quantum Data Centers

2026-06-11T21:09:46-07:00

Digital infrastructure operator BW Digital has entered into a strategic research partnership with the National University of Singapore’s College of Design and Engineering (NUS CDE). Announced at the DCD>Connect APAC 2026 conference, the 18-month collaborative program focuses on defining the underlying engineering frameworks and structural design criteria needed to host hybrid AI-quantum computing workloads within the tropical climates of Southeast Asia. The program is designed to bridge academic thermal research with real-world site selection, ensuring that regional data center builds can accommodate the severe environmental restrictions native to next-generation quantum processing units. The "Minimum Viable Infrastructure Envelope" and Environmental Stabilization The [...]

BW Digital and NUS CDE Launch Joint Framework for Tropical Quantum Data Centers2026-06-11T21:09:46-07:00

Pasqal Inaugurates Italy’s First Neutral-Atom Quantum Computer at CINECA Supercomputing Center

2026-06-11T20:57:58-07:00

Neutral-atom quantum hardware developer Pasqal has officially inaugurated its SOL quantum computer at the DAMA Technopole in Emilia-Romagna, Bologna. Hosted by CINECA, Italy's largest public supercomputing consortium and a core member of the Italian Research Center on HPC, Big Data, and Quantum Computing (ICSC), the deployment marks the installation of Italy's first operational neutral-atom quantum platform. Co-funded by the EuroHPC Joint Undertaking (JU) and Italy’s Ministry of University and Research, the system acts as Pasqal's third federated EuroHPC installation in Europe, following the active placement of identical hardware arrays at computing centers in France and Germany. The Orion QPU Architecture and [...]

Pasqal Inaugurates Italy’s First Neutral-Atom Quantum Computer at CINECA Supercomputing Center2026-06-11T20:57:58-07:00

Horizon Quantum Expands Hardware Testbed with 256-Qubit Trapped-Ion System Placement in Ireland

2026-06-11T18:26:09-07:00

Integrated software infrastructure pioneer Horizon Quantum Holdings Ltd. has announced plans to deploy its second hardware testbed location at its European headquarters in Dublin, Ireland. The facility will host a sixth-generation, chip-based 256-qubit trapped-ion system developed by IonQ. Backed by Ireland’s National Semiconductor Strategy (Silicon Island) and supported by IDA Ireland, the hardware expansion builds directly upon the company’s existing multi-vendor superconducting testbed array assembled at its Singapore headquarters. It aims to accelerate the deployment of high-fidelity, hardware-agnostic coding applications across the European Union deep-tech corridor. Trapped-Ion Architecture and Low-Abstraction Compilation Stacks The engineering milestone centers on the integration of IonQ’s [...]

Horizon Quantum Expands Hardware Testbed with 256-Qubit Trapped-Ion System Placement in Ireland2026-06-11T18:26:09-07:00

Nu Quantum Demonstrates Subsystem Erasure Tolerance in Networked QPU Architectures

2026-06-11T08:33:43-07:00

Distributed quantum hardware developer Nu Quantum Ltd. has reported structural mechanics and numerical simulations validating a fault-tolerant network framework capable of tolerating the complete failure of individual Quantum Processing Units (QPUs). Detailed in a technical manuscript deposited on the open-access arXiv repository, the research introduces a distributed quantum error correction (QEC) paradigm that handles catastrophic hardware node dropouts as correctable localized erasures. By shifting away from large monolithic processors and instead encoding logical information across an interconnected multi-node network, the system prevents the permanent loss of quantum data, allowing continuous computation during both unscheduled subcomponent failures and routine hardware calibration. The [...]

Nu Quantum Demonstrates Subsystem Erasure Tolerance in Networked QPU Architectures2026-06-11T08:33:43-07:00
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