Chart Showing Yield Results of a Sample 300 mm Intel Spin Qubit Wafer

Although we hear about many different device parameters from developers of quantum hardware, one important parameter we don’t hear about very much is device yield. For some of the quantum hardware developers that are early in their development cycles we suspect these yields may still be quite low. Although it is possible to build up a quantum processor from a few hero devices that are cherry-picked from a large number of runs, it is not very cost effective. And for quantum computing to reach its full potential the industry will eventually have to evolve from a development goal of getting a processor to run at all to a goal of reducing the cost to make the processor affordable to a larger user base. After all, If it takes $620 million to create more quantum processors in the future, the resulting market for QC won’t grow nearly to the size that we expect.

One company that understands this very well due to their semiconductor heritage is Intel Corporation and you can see this in the way they are approaching their quantum R&D. In the semiconductor world, the cost of a chip is a function of transistor size and the number of transistors you can fit on the die. So die area per transistor is a critical parameter. Extending this reasoning to quantum results in Intel choosing to use spin qubits instead of something like superconducting qubits because the advantage in die area per qubit is many orders of magnitude.

But to take advantage of the better die area, the qubits still need to exhibit high coherence times and gate fidelities in order to be competitive. In order to accelerate the development of manufacturing process to achieve this, Intel took another concept from semiconductor manufacturing and partnered with BlueFors and Afore to develop a custom cryogenic wafer prober. This machine can load and cool test wafers to a temperature of 1.6 K in roughly two hours and enable rapid testing of the thousands of spin qubits on the 300 mm wafer.

Intel has been working with their Tunnel Falls chip that has 12 quantum dot sites arranged in a linear array and recently published a paper describing their progress in achieving high spin qubit fidelity and uniformity in single electron control. Although Intel is taking advantage of the capabilities of its high volume semiconductor fabrication facility, they do need to make some changes in the process for optimizing the qubits. For example, Intel’s spin qubits are built upon a base wafer that has a Si/Ge epitaxy layer in order to reduce the disorder of the qubits. Standard semiconductors are built on a more traditional Si-Mos layer.

As a measure of their progress, you can view the chart above which shows Intel achieving a 96% yield rate on a wafer containing multiple chips with their 12 quantum dot array. One of the future steps that Intel will need to take in their development is to move from a linear chain of qubits to a 2D structure which will provide more connectivity and allow them to scale up the number of qubits. They intend on achieving this by adding more interconnect layers to the wafer process.

For more technical details about their progress, you can view the technical paper posted in Nature here and a blog article summarizing their progress that has been posted on Intel’s website here.

May 6, 2024