NTT Corporation, in collaboration with The University of Tokyo, Kyushu University, and RIKEN, has introduced a load-store architecture for quantum computing, separating memory and processing units to address scalability and resource efficiency challenges. This design replaces traditional quantum circuit-based approaches, reducing hardware resource requirements by approximately 40% while achieving up to 90% memory efficiency in practical scenarios. The architecture leverages row access and point access quantum memory methods, minimizing computation time increases to around 5% compared to conventional designs.
The load-store architecture enables portable programs, improving compatibility across different quantum hardware configurations. By abstracting memory and processing, the design simplifies program development and enhances scalability, addressing inefficiencies in traditional quantum circuits, where only 44% to 67% of hardware is utilized for calculations. This approach also supports advancements in error correction, programming languages, and compilation optimization, fostering parallel research in quantum computing.
The findings, presented at the 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA-31), demonstrate the effectiveness of classical computing concepts like load, store, and cache in quantum systems. This architecture is expected to accelerate the development of practical, fault-tolerant quantum computers by enabling efficient hardware utilization and promoting compatibility across evolving quantum technologies.
For more details, the original announcement by NTT (in Japanese) is available here. A technical paper has been posted on arXiv and can be accessed here.
March 3, 2025
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