A very important ratio for fault tolerant quantum computers is the Physical-to-Logical ratio. The represents the number of physical qubits needed to implement a logical qubit. The lower this ratio is, the better because it makes it easier to implement in hardware, reduces the cost of the machine, and many other things. The problem is that with many of the quantum error correction codes that have been developed, the number is quite high. It could be 1000:1 or even higher.
One of the reasons quantum error correction is harder than classical error correction is that many quantum processors can suffer from two different types of errors which need to be corrected known as bit flips and phase flips. Classical computers, on the other hand, are only plagued only by bit flip errors. This greatly increases the number of physical qubits needed to implement a quantum error correcting code.
Alice & Bob was formed to pursue what are known as Cat qubits. This technology works by using a hardware architecture that virtually eliminates bit flips so that a quantum error correcting code only needs to implement something that corrects for phase flips. Amazon is also researching superconducting quantum processors based upon Cat qubits. Using this approach reduces the number of physical qubits needed by the factor of a square root. In addition, with this new research they have gone one step further and implemented an error correction code known as Low Density Parity Check (LDPC) which is much more efficient than the commonly used surface code. The traditional problem with LDPC codes has been that it requires qubits to be able to connect to other qubits when are farther away, termed long range connectivity. An advantage of the surface code is that it can be implemented with qubits that only connect to their nearest neighbor. The breakthrough is that Alice & Bob, working with researchers at Inria, have been able to come up with an LDPC code that can be implemented with short range connectivity making it much more practical. Putting Cat qubits and LDPC together, the team has developed an architecture that can implement 100 logical qubits with about 1500 physical qubits to obtain a Physical-to-Logical ratio of 15:1. That is much better than the 1000:1 ratio we mentioned earlier.
An additional aspect described in their research paper which is not often discussed in other quantum error correction papers, is that they have also developed a way of implementing a universal gate set using two layers of chips attached together using flip chip technology. A universal set is needed in order to implement any potential quantum algorithm and implementing it is much more complex. The paper goes into detail on who they intend to do this. The architecture consist of what they call a Memory layer that uses the LDPC code as discussed below and another chip for implementing the gates called the Computing layer which uses a repetition code as shown in the diagram below.
So these advances look very promising, but one should remember that this architecture is still theoretical and needs to be proven out with real hardware. Sometimes real hardware does not work exactly the same way that is predicted by the theory. But a demonstration may come out soon because Alice & Bob taped out a test chip last month that may allow them to show how the theory works in practice once they have finished testing the chip.
So overall, progress is being made at a rapid pace with quantum error correction. If the pace keeps up it may mean that fault tolerant quantum computers could become available within the next few years and much soon than we previously thought. Even though some of the first machines may only support a few hundred logical qubits, that may be large enough for users to run a few applications that provide a commercial quantum advantage.
For more information about this development, you can view a press release issued by Alice & Bob here, a video on YouTube posted by Alice & Bob explaining the development here, and a technical paper posted on arXiv here.
January 23, 2024
