One of the issues with scaling up superconducting or spin qubit quantum processor chips is that in order to control the qubits, one needs to route individual connections to each of the qubits to carry the electrical control signals. So when the number of qubits gets into the thousands, tens of thousands, or more, the quantum hardware engineers run into a major mechanical engineering challenge on how to route those wires.
Several companies including Microsoft, Google, and others have been working on cryoCMOS control chips that operate inside the dilution refrigerator so they can be near the qubit chips. But often, these chips will run at 4 degrees kelvin while the qubit chips will run at the coldest level at about 10 millikelvin. So although the problem is lessened, the engineers still need to develop ways to connect the last few inches.
But now Intel has developed an innovative solution that may be able to provide a solution. First, they are working on creating a two-level solution that still has a control chip called Horse Ridge II running at the 4 kelvin level, but they added a simple millikelvin cryoCMOS chip called Pando Tree that sits right next to the qubit chip or may even be further integrated using Intel’s advanced packaging technology and Intel’s Foundry Flip Chip Ball Grid Array 2D (FCBGA 2D). The Pando chip is simple and provides demultiplexing for two input analog voltages for DC bias and high-speed voltage pulsing. It only needs log(N) input signals coming from the Horse Ridge II chip to control N qubits. It also is a nice solution because circuit portions of the control chip like D/A and A/D converters can consume a bit of power and overwhelm the cooling capacity of a dilution fridge at 10 millikelvin. By placing those portions of the circuit at the 4 kelvin level there is orders of magnitude more cooling capacity to handle the heat those circuits generate. Intel is looking to use this dual-level control chip strategy to enable the scaling of their quantum processors to millions of qubits.
Intel has published a blog describing this new chip and how it fits into the architecture of the system that can be viewed here. They also made a presentation about this chip at the 2024 IEEE Symposium on VLSI Technology & Circuits and you can see an abstract of the talk here.
June 21, 2024