Photo Showing the Chip at the Heart of the H2 Processor with the “Racetrack” Topology for the Ions

Quantinuum has announced the H2 processor that they have had on their roadmap for a while. The processor currently has 32 qubits and the capacity to process gate operations in four zones simultaneously. It continues with Quantinuum’s lead in qubit quality measures and even improves upon their leading Quantum Volume (QV) measure previously held by their H1-1 model with a QV of 65,536 on the H2 versus the previous 32,768 on the H1-1. The system is available now directly through Quantinuum and will also be available through the Microsoft Azure quantum cloud in June. Like Quantinuum’s development approach with the H1 generation, the company expects it will be continuing to improve various models of the H2 over the next year or two and hopes to have a version with more than 50 qubits in 2024. Like the H1 generation, the H2 also features all-to-all connectivity for the qubits and also mid-circuit measurement. A paper titled A Race Track Trapped-Ion Quantum Processor describing the H2 has also been posted on the arXiv.

While they are continuing to work on improved versions of the H2 generation, Quantinuum has already set in place a roadmap for generations H3, H4, and H5. Some of the technologies they will be using for these include a grid based ion topology that will require the movement of ions around 90 degree corners instead of just a linear movement, integrated optics using photonic integrated circuits, shrinking the control logic using application specific integrated circuits (ASICS), and further increasing the scale by creating modular ion trap chips that can be coupled together.

In order to demonstrate the capabilities of their ion trap based architecture, Quantinuum has also posted several technical papers describing some original research performed using the machine. First, they have demonstrated creating a 32 qubit GHZ state. This is a non-classical state with all 32 qubits globally entangled and is the largest such GHZ state anyone has implemented so far. Next, in collaboration with Harvard and Caltech, they have created Non-Abelian Topological Order and demonstrated control of its anyons. This has the potential to be used in fault tolerant computers. Developing a fault tolerant architecture around topological principles can potentially be more robust against errors because a state is not encoded by the physical state of a bunch of qubits, but rather as the overall topology of how qubits are connected together. It could potentially provide significant advantages over other error correction codes, such as the surface code, and Quantinuum believes that their architecture is much better suited to support this code than other architectures. Microsoft is also researching topological based qubits, but they are pursuing a different physical approach based upon splitting a qubit between two Majorana zero modes (MZM). Quantinuum has posted a research paper on arXiv about their research titled Creation of Non-Abelian Topological Order and Anyons on a Trapped-Ion Processor.

Other research papers based upon experiments run on the H2 include one titled Exploring the neighborhood of 1-layer QAOA with Instantaneous Quantum Polynomial circuits that takes advantage of key features of the Quantinuum processors such as the native parameterized two-qubit gates and the all-to-all connectivity to create an improved variational quantum algorithm for solving combinatorial optimization problems. Another piece of early research performed on the H2 processor includes a paper from the Global Technology Applied Research at JPMorgan Chase that describes a quantum algorithm design for portfolio optimization.

To read more about Quantinuum’s H2 announcement, you can view a copy of the press release here. Quantinuum has also created a web page with links to all the technical papers, blog posts, and data sheets related to the H2 available here.

May 9, 2023