Two of the biggest challenges in creating a next generation, higher performance quantum computer is obtaining high levels of qubit quality and also scaling up the numbers of qubits to meaningful levels. An additional challenge is to improve the gate delays so the operations can run faster and reduce the runtime for complicated algorithms.

Quantinuum has recently shown a couple of papers that show progress in these areas. As shown in the diagram above, their latest released quantum process is called the H2 which has 32 qubits arranged in what they call a racetrack topology. Implementing more qubits using this architecture is problematical because of issues with die area, control wires, and ion shuttling. So, as shown in the diagram, their next generation of processor, called the H3, will use a grid layout. This generation will have many more qubits along with many other advantages.

But another issue that needs to be solved as the qubits scale up is managing the number of wires needed to control the qubits. The current generation of ion trap requires several control lines per qubits. The company indicates that in some cases there could be as many as 20 analog lines per qubits. Such an approach would become unmanageable for a device with a large number of qubits. In this latest research Quantinuum has identified and tested a technique to limit the number of lines to one digital wire per qubits plus a fixed number of analog lines which does not scale up as the qubits increase.

The key to this wiring reduction is something that Quantinuum calls a C2LR (Center-to-Left-or-Right) primitive which provides a conditional shift to the left or right depending on the state of the digital control wire as shown below. In the picture below, V1 and V2 represent the analog signals which are globally routed to all qubits and the digital control line control a switch to determine whether the well translates to either the left or the right.

The company reports that they are able to achieve swap rates of 2.5 kHz with very low levels of heating. In addition, they point out that the grid approach allows them to rearrange the qubits much faster than if they were implemented in the linear or racetrack topology. More information about this new development from Quantinuum is available in a news release here, a blog post here, and a technical paper posted on arXiv here.

A second development from Quantinuum is an improvement in how the ions are cooled. Ion traps do not use dilution refrigerators like the superconducting systems have, but rather use carefully tuned laser pulses. Their new approach which they call Phonon Rapid Adiabatic Passage (PHRAP) provides a way of speeding up the ion cooling by an order of magnitude. Better cooling will result in higher levels of gate fidelity and will also improve gate delays and overall program runtime for an end user. Additional information about this new development to cool the ions can be seen in a LinkedIn post here and another technical paper posted on arXiv here.

March 9, 2024