If you want to better understand what some of the next developments needed to continue scaling up the size of quantum computers, you should look at the picture below.

Cabling in the Google Sycamore Processor (Credit: Google)

This design requires the routing of approximately 200 coaxial cables that start at room temperature (300 K degrees) and go down the dilution refrigerator to the qubit chip which operates at about 10 millikelvin.  The mechanical engineering challenges for such a design are quite significant.  In fact, Google mentioned at the recent Q2B conference that the reason the Sycamore is a 53 qubit processor instead of 54 is not due to a bad qubit, but rather the fact that one of the cables is broken! Now imagine trying to extend this design to 1000 qubits.  Besides the physical space challenges involved with routing thousands of wires, there are also the thermal as well as crosstalk/signal integrity issues that would arise. So a discrete cabling approach will no longer be viable and new approaches need to be developed.

So this is where cryo-CMOS control chips fit in and several recent announcements show progress in this area.  The first is a development from Intel called Horse Ridge. Horse Ridge is a highly integrated, mixed-signal SOC built with Intel’s 22nm FinFET technology designed specifically to control both the superconducting and spin qubit technologies that Intel is developing.  It currently runs at 4 Kelvin which is within the range of possible operation of spin qubits, but would require some routing of signals from that level to the 15 millikelvin level required for superconducting qubits.

Although Intel is not releasing full technical details on this chip yet, they did tell us they will be presenting it at the International Solid-State Circuits Conference (ISSCC) in February 2020 in San Francisco.  At this time, the chip is intended for Intel’s internal use only and a picture of this chip on a test board is shown below.

Stefano Pellerano, principal engineer at Intel Labs, holds Horse Ridge. (Credit: Walden Kirsch/Intel Corporation)

The second disclosure has come from Microsoft’s team in Australia along with their collaborators at Purdue University.  They have developed a qubit control chip with over 100,000 transistors that operates at roughly the 100 millikelvin level.  It is implemented in a 28 nm fully depleted silion-on-insulator (FDSOI) technology and Microsoft is claiming this will allow them to control up to 50,000 qubits with just three wires. Microsoft has posted two technical papers describing this chip (links are posted at the end of this article) and the picture below shows how it was recently displayed it in a glass case at the Q2B Conference in San Jose.

Microsoft’s Cryo-CMOS Qubit Control Chip on a Test Board

Finally we should note that Google presented a paper earlier this year at ISSCC 2019 on “A 28nm Bulk-CMOS 4-to-8GHz <2mW Cryogenic Pulse Modulator for Scalable Quantum Computing”.  Although the Google chip was a prototype chip that appeared to only support one qubit, its operation temperature was 3 Kelvin will certainly be used to provide valuable information for development of larger chips.


If you want to see more details about the chips mentioned in this article, here are the links.

· Intel’s News Release on their Horse Ridge Chip
· Microsoft’s First Paper on their Cryo-CMOS Control Chip
· Microsoft’s Second Paper With Additional Information on Cryo-CMOS Control Interfaces
· Google’s Paper on their Cryogenic Pulse Modulator Prototype

December 13, 2019