We’ve talked in these pages about technology that is used at what we call the “Mid-Stack”. This includes the control electronics to control the qubits and the software algorithms to direct the control electronics and implement a variety of functions including calibration, error mitigation, etc. We’ve have also discuss quantum error correction techniques that will take a grouping of physical qubits with a certain physical error rate and use them to implement a logical qubit to achieve a lower logical error rate. Examples of such error correction codes include the surface code, color code, low density parity check (LDPC) and many others. It is expected that in the long term, such error correction codes will become mandatory for achieving the large, complex problems that quantum computers are expected to tackle.
But when a quantum computer starts using error correction techniques, it will make the Mid-Stack control solutions more complex. These codes are based upon a process where a gate operation is performed on the grouping of physical qubits, then some of them are measured to create a error syndrome, the error syndrome is analyzed classically to determine if any errors occurred, and correction action, if needed, is fed back to the quantum circuitry so that the qubits in error can be reset to a valid state. The challenge in this process is that it needs to be performed very quickly in real time within the coherence time of the qubit, You can’t apply correction to a qubit that has already decohered. For a superconducting system, this would require performing this process in just a microseconds. For ion trapped processors, the time is a little longer because of their greater coherence.
Because of these time constraints, the classical processing to decode the error cannot be performed by a standard classical computer connected to the quantum processor in a hybrid setup. For error correction, the latencies are just too great. So researchers are looking at dedicated electronics for this function that are designed to be very fast and placed as close to the qubits as possible. And this is what Riverlane has developed with the dedicated qubit controller chip. Riverlane has two devices to implement this function. The first is called the DD1 which is actually IP, programmed in Verilog, that can be fit into a Xilinx FPGA chip that would be integrated with the control electronics. FPGA”s provide the flexibility to make changes in the design just by loading in new Verilog code. It also allows a developer of the control electronics to include other control electronics functions on the same FPGA. Up to four decoder cores can be used together and Riverlane has designs that can implement a rotated planar surface code across a range of code distances from 3 to 23 while still maintaining low power levels and achieving decoding frequencies greater than one megahertz.
Although implementation of a decoder chip with an FPGA is convenient, a more efficient implementation is to embed the logic inside a dedicated ASIC chip. ASIC typically have even faster logic, smaller die areas, and are cheaper when used in high volumes. But they lack the flexibility of an FPGA and the non-recurring engineering (NRE) cost to modify a design is very high. The second design that Riverlane announced is called the DD0A. This is a test chip to show how the decoder can be implemented in an ASIC. It uses an earlier version of the decoder logic so it would not be ready for production use. However, Riverlane is planning on combining the technology it developed in the DD1 and the DD0A into a future ASIC called the DD1A anticipated in 2024.
Riverlane states they their technology will achieve the best balance between the speed, accuracy, cost, hardware, and power requirements, for an quantum error decoder and it can be used with superconducting, trapped ion, and neutral atom based quantum processors. They are working with quantum hardware companies to help evaluate Riverlane’s decoder technology and expect to test it with live hardware in Q4 of this year.
Riverlane has published several documents that describe these products in more detail. A press announcement is available here, blog articles describing the product and Riverlane’s decoder roadmap can be found here and here, a web page for the DD1 is here, a more detailed data sheet for the DD1 can be found here, and a technical pre-print posted on arXiv about their technology is available here.
September 13, 2023