We had previously reported about efforts by Intel, Microsoft, and Google to develop cryo-CMOS quantum control chips to help minimize the tangle of cables that are needed in the current generation of quantum computers. Today, Intel and QuTech revealed additional details of their chip, code-named “Horse Ridge”, at the International Solid State Circuits Conference (ISSCC). In a paper titled “A Scalable Cryo-CMOS 2-to-20 GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers” they describe a chip that can provide the requisite microwave control signals for up to 128 qubits with a wide frequency range from 2-20 Ghz that can support both superconducting (transmons) as well as spin qubits. The transmons typically operate around 6 to7 GHz, while spin qubits operate around 13 to 20 GHz.
The chip is arranged with four RF channels with each controlling up to 32 qubits. Each RF channel has 32 numerically controlled direct digital synthesis oscillators that can generate the required frequency with high precision. The chip is programmable and contains an on-board SRAM that can define 8 instructions per qubit to specify the exact pulse shaping needed for that qubit. Special care has been taken to maintain a high level of control signal fidelity with attention paid to reducing phase shift that can cause crosstalk between qubits. Although the chip current operates at a temperature of 3 Kelvin, they indicated that they are exploring silicon spin qubit technology that can operate as high as 1 Kelvin. If they achieve this they may be able to modify the control chip to run at 1 Kelvin which would pave the way for additional integration.
Intel has provide the table below that compares their Horse Ridge chip with other efforts. The column labelled ISSCC’19 was presented by a team from Google and the column labelled RSI’17 was developed by a team from Raytheon BBN technologies.
February 18, 2020